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Front End Implementation Engineer Intern
SAN JOSE CA 95115
Category: Other
  • Your pay will be discussed at your interview

Job code: lhw-e0-89772543

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Xilinx, Inc.

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  Job posted:   Thu May 17, 2018
  Distance to work:   ? miles
       
  1 Views, 0 Applications  
 
Front End Implementation Engineer Intern
Xilinx is the leading provider of All Programmable FPGAs, SoCs, MPSoCs and 3DICs. Xilinx's all-programmable devices are designed into tens of thousands of products that improve the quality of the everyday lives of billions of people worldwide. For over 30 years, Xilinx has been behind some of the greatest advancements in technology and science - from the industry's first fabless semiconductor model to the NASA Curiosity Mars Rover, to today's autonomous vehicles and hyperscale data centers. Xilinx uniquely enables applications that are both software-defined, yet hardware optimized - enabling smart, connected and differentiated applications across technology's biggest megatrends, including Machine Learning, 5G Wireless, Embedded Vision, Industrial IoT and Cloud Computing and more.
If you are a passionate, innovative and an out-of-the-box thinker that enjoys challenging projects, Xilinx is the right place for you. Our global team is growing and we are looking for bold, collaborative, and creative people to help deliver groundbreaking technologies that enable our customers to differentiate. Come do your best work and live your best life through collaboration, wellness and giving back to your community as a member of the ONEXILINX team.
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Job Description :**
Xilinx is looking for a driven, self-motivated intern for the development of high-performance IP blocks in the company's next generation FPGA product. Successful candidates will help the RTL design team meet their quality metrics regarding standard LINT, CDC, SDC, STA, and DFT checks as well as other custom quality checks. The position requires candidates to run regular tool regressions, analyze results, and drive issues to closure with the RTL design team.
**Qualification :**
Applicants must be currently pursuing a bachelor's or master's degree in Electrical Engineering or related field.
Required Experience:
* Proficiency with TCL shell scripting
* Synopsys Design Compiler and/or PrimeTime experience
* Exposure to SDC constraint development and debug
* Exposure to timing closure process including ECO generation/evaluation
Optional Experience:
* Conformal LEC (for verification of ECO's)
* Mentor Questa CDC (Zero In)
* Spyglass LINT and DFT
* Fishtail constraint verification
* Using databases such as Mongodb to store and query design metrics
* Generation of HTML based dashboards
Highly motivated candidates with strong written and verbal communication skills and structured, well-organized work habits are desired.

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